The inventive concept relates to semiconductor memory devices. More particularly, the inventive concept relates to semiconductor memory devices implemented with a multi-chip package (MCP) structure. Such MCP semiconductor memory devices provide active termination to a common data I/O bus.
Many electronic systems include a controller and memory device(s) configured to exchange data via one or more data bus(es). The use of data buses in such systems is well known as are the problems associated with properly terminating the controller and memory devices to a bus. Improperly terminated signal lines within a bus will generate noise in the form of signal reflections. There are many different ways to terminate a data bus signal line, by a resistor connected between the signal line and a power supply node is common.
For incorporating systems, such as computers, signal line terminations may be provided using (relatively large) external resistors disposed on a printed circuit board (i.e., a computer system motherboard). Thus, a signal line interconnecting integrated circuits (ICs) may be effectively terminated by selecting an external resistor having a desired impedance. When the impedance of the selected external resistor matches the signal line impedance, signal reflections rarely occur in a meaningful way. However, external resistors disposed on a system board for each one of a great multiplicity of signal lines occupy a large amount physical space.
As an alternative to the use of external resistors, so-called “on-chip termination” or “on-die termination” (ODT) may be used. Such signal line termination circuits are commonly referred to as “active termination units”, and may be used for many of the ICs forming contemporary consumer electronics. Active termination is a method in which a termination resistor is inserted into, for example, each of a memory device and a controller chip and is then turned ON/OFF as needed.
Methods of turning ON/OFF an active termination unit may vary according to the configuration of the memory device and related input commands. For example, one method of turning ON/OFF an active termination unit provides that a memory controller apply various configuration setting signals to a mode register within a connected memory device. Another method of turning ON/OFF an active termination unit identifies whether a current memory system command is directed to a particular memory device.
If a semiconductor memory device has a multi-chip package (MCP) structure in which two or more memory chips share a common data I/O bus, then each of the memory chips may turn ON a related active termination unit when a corresponding chip enable (CE) signal is provided to the memory chip. This approach to memory system control is referred to as ‘self-termination’. Also, each of the memory chips may turn ON a related active termination unit when a CE signal is generated within the memory chip itself. This operation is referred to as ‘other termination’ and is essentially the opposite of the self-termination approach.
However, when “other termination” is performed by a memory device having an MCP structure, for example, when a first memory chip and a second memory chip are disposed in the memory device and the second memory chip is activated in response to a corresponding CE signal internally generated within the second memory chip, then the first memory chip turns ON a termination resistor included in the first memory chip since a corresponding CE signal generated within the first memory chip itself is not activated. In this case, when the termination resistor included in the first memory chip is turned ON, a data input/output (I/O) line is terminated (i.e., self-termination occurs in the accessed second memory chip since a data IO line is shared between the first and second memory chips).
Accordingly, a controller chip set should individually and independently supply a control signal to the memory chips included within a MCP semiconductor memory device in order to differentiate said control signals. Unfortunately, this result increases the number of terminals for individually supplying control signals from the controller in a chip set.